| Title |
Test Methodology for Multiple Clocks Single Capture Scan Design based on JTAG IEEE1149.1 Standard |
| Authors |
김인수(Kim, In-Soo) ; 민형복(Min, Hyoung-Bok) |
| Keywords |
Boundary Scan ; Clock Group Register ; Internal Scan Chain ; Multiple Clock System ; Scan Design |
| Abstract |
Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits. |