| Title |
The Effective ROM Design for Area and Power Dissipation Reduction |
| Authors |
정기상(Jung, Ki-Sang) ; 김용은(Kim, Yong-En) ; 조성익(Cho, Seong-Ik) |
| Abstract |
In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method. |