| Title |
The Gain Enhancement of 1.8V CMOS Self-bias High-speed Differential Amplifier by the Parallel Connection Method |
| Keywords |
Self-bias ; Differential amplifier ; Internal biasing ; High-speed analog ; Complement gain |
| Abstract |
In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V 0.8μm CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively. |