| Title |
Phase-Locked Loops using Digital Calibration Technique with counter |
| Authors |
정찬희(Jeong, Chan-Hui) ; Abdullah, Ammar(Abdullah, Ammar) ; 이관주(Lee, Kwan-Joo) ; 김훈기(Kim, Hoon-Ki) ; 김수원(Kim, Soo-Won) |
| DOI |
https://doi.org/10.5370/KIEE.2011.60.2.320 |
| Keywords |
Charge pump(CP) mismatch ; Digital calibration ; Charge pump phase-locked loop(CPPLL) |
| Abstract |
A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm^2. |