| Title |
Design of Wide-range All Digital Clock and Data Recovery Circuit |
| Authors |
고귀한(Go, Gwi-Han) ; 정기상(Jung, Ki-Sang) ; 김강직(Kim, Kang-Jik) ; 조성익(Cho, Seong-Ik) |
| DOI |
https://doi.org/10.5370/KIEE.2012.61.11.1695 |
| Keywords |
Wide-range CDR(Clock Data Recovery) ; All digital |
| Abstract |
This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per 2π/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool. |