| Title |
TSV Defect Detection Method Using On-Chip Testing Logics |
| DOI |
https://doi.org/10.5370/KIEE.2014.63.12.1710 |
| Keywords |
TSV test ; On-chip test logic ; Pre-bond test ; Post-bond test ; 3D-IC |
| Abstract |
In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection. |