| Title |
Design of 1.2 kV SiC Double Trench MOSFETs for a Low On-Resistance Through Optimized Current Spreading Layer Concentration |
| Authors |
김진훈(Jinhun Kim) ; 윤효원(Hyowon Yoon) ; 박영은(Yeongeun Park) ; 김상엽(Sangyeob Kim) ; 강규혁(Gyuhyeok Kang) ; 백두산(Dusan Baek) ; 박수민(Sumin Park) ; 석오균(Ogyun Seok) |
| DOI |
https://doi.org/10.5370/KIEE.2024.73.8.1339 |
| Keywords |
Neural Network; SiC; double trench MOSFET; CSL; electric field crowding; depletion |
| Abstract |
SiC double trench MOSFETs have the advantage of generating a deep P+ layers through the trench source, effectively mitigating electric field crowding at the bottom edge of the gate oxide. However, the depletion region induced by the deep P+ layers narrows the current path between the gate and P+ , resulting in an increase in the on-resistance. In this study, we addressed this problem by introducing CSLs through ion implantation in the 1.2 kV SiC double trench MOSFETs. CSL concentration optimization resulted in a 3.92 % decrease in on-resistance and a 3.19 % increase in the figure of merit. Therefore, the SiC double trench MOSFET with optimized CSL concentration has improved on-resistance characteristics and figure of merit compared to the conventional structure. |